The present invention generally relates to the field of microelectromechanical systems, and more particularly to creating a layout of at least a portion of such a microelectromechanical system.
There are a number of microfabrication technologies that have been utilized for making microstructures (e.g., micromechanical devices, microelectromechanical devices) by what may be characterized as micromachining, including LIGA (Lithography, Galvonoforming, Abforming), SLIGA (sacrificial LIGA), bulk micromachining, surface micromachining, micro electrodischarge machining (EDM), laser micromachining, 3-D stereolithography, and other techniques. Bulk micromachining has been utilized for making relatively simple micromechanical structures. Bulk micromachining generally entails cutting or machining a bulk substrate using an appropriate etchant (e.g., using liquid crystal-plane selective etchants; using deep reactive ion etching techniques). Another micromachining technique that allows for the formation of significantly more complex microstructures is surface micromachining. Surface micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate (e.g., a silicon wafer) which functions as the foundation for the resulting microstructure. Various patterning operations (collectively including masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called xe2x80x9creleasingxe2x80x9d the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate.
It has been proposed to fabricate various types of optical switch configurations using various micromachining fabrication techniques. One of the issues regarding these types of optical switches is the number of mirrors that may be placed on a die. A die is commonly referred to as that area defined by one field of a stepper that is utilized to lay out the die. Reducing the size of the mirrors in order to realize the desired number of mirrors on a die may present various types of issues. For instance, there are of course practical limits as to how small the mirrors can be fabricated, which thereby limits the number of ports for the optical switch. Also, the optical requirements of the system using the mirrors may require mirrors larger than some minimum size. Therefore, it may not be possible to fabricate the optical switch with a certain number of ports using a single die. This presents a challenge regarding how to route electrical signals.
A first aspect of the present invention generally relates to a method for making a chip. An initial portion of the first aspect relates to configuring or defining or creating a layout for a die. This die may be characterized as having a first configuration. This first configuration is that the die includes a plurality of rows of a plurality of mirror assemblies, a plurality of off-chip electrical contacts associated with each of these rows, and an electrical trace bus that is located between at least some adjacent pairs of mirror assemblies. Each electrical trace bus is electrically interconnected with at least some of the mirror assemblies in at least one of the adjacently disposed rows of mirror assemblies (i.e., a row that borders the electrical trace bus or confines the same).
The first aspect includes forming a plurality of die on the wafer that each have the above-noted first configuration. A chip may then be separated from the wafer. More specifically, a chip is separated from the wafer such that a first dimension for the chip is an integer multiple of the die, and further such that a second dimension for the chip is an integer multiple of the rows of mirror assemblies. The first and second dimensions are orthogonal to each other, and may be characterized as defining a plan view of a chip.
Various refinements exist of the features noted in relation to the first aspect of the present invention. Further features may also be incorporated in the first aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. A xe2x80x9cchipxe2x80x9d as used herein means a continuous section of a wafer that may be sawed, diced, or otherwise separated in any appropriate manner from a wafer. As used herein, a xe2x80x9cdiexe2x80x9d means an area encompassed by a single exposure field of a photolithographic stepper.
The various mirror assemblies of the first aspect each may include a mirror and at least one actuator that is interconnected with its corresponding mirror in an appropriate manner to control/establish the position thereof to provide a desired/required optical function. The layout of the mirror assemblies on each of the die may assume a number of arrangements. In one embodiment, a center of each mirror in a given row is disposed along a common reference line. In another embodiment, a center of each mirror in a given row is alternately disposed on opposite sides of a central reference line. In either case, the mirrors in a given row may be equally spaced in relation to a direction in which the row at least generally extends. Preferably, at least the width dimension of the chip is an integer multiple of the spacing between adjacent mirrors in a given row. Preferably, the same mirror-to-mirror spacing is used in each row of each die.
A plurality of off-chip electrical contacts may be disposed at least generally beyond the end of each of the plurality of rows of mirror assemblies in accordance with the first aspect. In the case where each mirror assembly includes at least one mirror as noted above, each actuator may be addressed by a different off-chip electrical contact. In one embodiment, one-half of the actuators in a given row are independently addressable from the off-chip electrical contacts on one side of the chip, while the other half of the actuators are independently addressable from the off-chip electrical contacts on another side of the chip (e.g., on the opposite side of the chip). That is, preferably each individual actuator of each mirror assembly is preferably independently addressable from a perimeter region of a chip in accordance with the first aspect.
In one embodiment of the first aspect, each electrical trace bus is interconnected with at least some of the microstructure assemblies in one of the two rows between which the electrical trace bus is located, and none of the microstructure assemblies in the other of these two rows. In another embodiment, each electrical trace bus is interconnected with at least some of the microstructure assemblies in both of the two rows between which the electrical trace bus is located. In yet another embodiment, none of the plurality of electrical traces within any electrical trace bus cross over each other.
Consider the case where each of the plurality of rows of mirror assemblies in accordance with the first aspect at least generally extend in a first direction. In one embodiment, this collection of multiple rows of mirror assemblies collectively spans less than one die in a second direction that is perpendicular to the first direction. That is, a chip in accordance with the first aspect may have a chip height that is less than that of a single die on the wafer from which a chip is formed. In another embodiment, this collection of multiple rows of mirror assemblies collectively spans at least one die in a second direction that is perpendicular to the noted first direction. Stated another way and where each row of mirror assemblies extends in a direction corresponding with a die width, a chip in accordance with the first aspect may include at least one die height, and thereby encompasses having multiple die heights. Another embodiment has the plurality of rows of mirror assemblies collectively span a non-integer number of die in a second direction that is perpendicular to the noted first direction. Stated another way and where each row of mirror assemblies extends in a direction corresponding with a die width, the chip may include at least one partial die height (including having at least one full die height in combination with at least one partial die height, and less than a single die height as noted above).
The plurality of die in the case of the first aspect may be formed on the wafer in a plurality of die rows and a plurality of die columns. Each adjacent pair of die in each of the plurality of die rows may be electrically interconnected when formed on the wafer and before the chip is separated from the wafer. In one embodiment, only adjacent die that are in the same row are electrically interconnected. That is, in one embodiment none of the adjacent die in any column are electrically interconnected when formed on the wafer. When a chip in accordance with the first aspect is separated from the wafer having the plurality of die rows and die columns, preferably the chip is dimensioned so as to take only complete die in a first dimension that corresponds with the direction in which the die rows extend on the wafer. However, the chip may be dimensioned so as to take one or more complete die, one or more partial die, or some combination thereof, in a second dimension that corresponds with the direction in which the die columns extend on the wafer.
A second aspect of the present invention is embodied by a method for creating a layout of a microelectromechanical system. A method includes drawing a first unit cell precursor that has a plurality of electrical traces. A copy of this first unit cell precursor is made, and which may be characterized as a first unit cell precursor copy. The first unit cell precursor and the first unit cell precursor copy are disposed in interfacing relation. The various electrical traces are routed within the first unit cell such that when the first unit cell and first unit cell precursor are disposed in appropriate interfacing relation, the appropriate electrical traces in the first unit cell precursor are properly aligned with the appropriate electrical traces in the first unit cell precursor copy.
Various refinements exist of the features noted in relation to the second aspect of the present invention. Further features may also be incorporated in the second aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. The drawing of the first unit cell precursor may include defining at least a portion of the boundary of the first unit cell precursor by where at least some of the plurality of electrical traces terminate. For instance, first and second sides of the first unit cell precursor may be defined by where at least some of the plurality of the electrical traces terminate. In one embodiment, at least some of the electrical traces extend completely between the first and second sides. In another embodiment, at least some of the electrical traces terminate at a location other than the first and second side of the first unit cell precursor. For instance, the end of such an electrical trace may interconnect with an appropriate microstructure (e.g., an actuator of a mirror assembly) that is disposed at an interior location of the first unit cell precursor and that may be drawn in the first unit cell precursor along with the plurality of electrical traces. In one embodiment, there are an odd number of microstructures within the first unit cell precursor that are each electrically interconnected with a different electrical trace. As such, when the first unit cell precursor and first unit cell precursor copy are disposed in interfacing relation, the resultant first unit cell will have an even number of microstructures that are electrically interconnected with an electrical trace. This then allows one half of the microstructures to be addressed from one side of a chip layout defined by tiling a plurality of the first unit cells, and for the other half of the microstructures to be addressed from a different side of the chip layout.
In one embodiment of the second aspect, the first unit cell precursor copy is translated from the position of the first unit cell precursor prior to disposing the same interfacing relation. In another embodiment, the first unit cell precursor copy is not only translated in the above-noted manner, but rotated as well. That is, it may be necessary to rotate the first unit cell precursor copy from the position of the first unit cell precursor and to translate the first unit cell precursor copy from the position of the first unit cell precursor in order to appropriately align the relevant electrical traces of the first unit cell precursor with the relevant electrical traces of the first unit cell precursor copy. As such, the first unit cell precursor and the first unit cell precursor copy may be disposed in different orientations when disposed in interfacing relation. In any case, the first unit cell precursor and the first unit cell precursor copy may collectively define a unit cell that may be copied a plurality of times to define a desired microelectromechanical system or at least a portion thereof (e.g., at least an electrical trace bus, as well as such a bus and its electrically interconnected microstructures). For instance the first unit cell may have the plurality of electrical traces disposed in a manner that meets various boundary conditions that allows a plurality of units cells that are disposed in end-to-and relation to be appropriately electrically interconnected. In the event that a certain number of unit cells are used to define a chip, each electrical load-based microstructure may be separately addressed on a perimeter of such a chip.